Present memory systems (DDR1; DDR2; DDR3) provide the possibility of supplying the DIMM command/address bus transferring the command and address signals (CA) with only one version (copy) of the CA bus, for example via a hybrid-T or fly-by bus. With further increasing speeds and considering the high parallelism at the CA bus (for example up to 36 memory chips per CA bus), the conventional transfer of command and address signals is no longer possible.
A potential solution to the above-mentioned problem lies in using two copies of the CA bus. This, however, increases the pin number per memory channel (for example by 25 CA signals and the pins required for the necessary shielding). Because of the high bit rate on the data lines, a differential signal transfer is considered for successor technologies of the DDR3 system, for example for DDR4. For differential signal transfer, however, the number of pins required is distinctly higher, the implementation thereof being very difficult from a technical point of view (or causing high cost). This involves the pin number at the connector of the semiconductor memory module, the pin number at the memory controller and the routing on the motherboard.
Since, owing to the high bit rates of the successor technologies of the DDR system, only fly-by busses or point-to-point (P2P) busses will be possible, any clock signal required for synchronization must also be transferred differentially together with the CA signals.
The exemplary arrangement of DDR2 systems according to the state-of-the-art shown in the accompanying FIG. 4 is a schematic layout view of a DDR2 DIMM semiconductor memory module, wherein the CA signals CA coming from an external CA bus and the assigned clock signals Cl on the semiconductor circuit module are transferred to the DDR2 DIMM semiconductor memory module via a hybrid-T bus structure (the lines transferring the differential clock signals Cl are presented by broken lines and the lines transferring the differential CA signals are presented by dash-dotted lines). In the example, semiconductor memory chips 4 each storing eight data items D and an additional error correction chip (D-E-CC) 4a and additional passive components 5 are arranged on the DIMM semiconductor memory module. The data pertaining to the individual memory chips 4 and to the D-E-CC chip 4a is each transferred with a width of eight bits, thus being assigned to 72 connector locations or pin contacts 8 in case of this semiconductor module.
The accompanying FIG. 5 is an exemplary schematic view of a potential semiconductor memory module for the DDR4 system, wherein use is being made of two copies of the CA bus in accordance with the above-mentioned theoretical solution. In the example, the differentially supplied CA signals CA including the clock signals Cl require 25×2 (×2) connector locations or pin contacts 8 for a 2N timing. The lines required for shielding are also necessary. In the example shown in FIG. 5, the write and read data is supplied to each memory chip 4, 4a of the memory channel arranged to the left of the semiconductor memory module and of the memory channel arranged to the right of the semiconductor memory module with a width of two bits and differentially; this results in an X2-based DDR4 DIMM with 2N timing of the CA signals. In case of such a semiconductor memory module which comprises several memory channels or memory banks, the wide routing of the twice as many CA and Cl lines on the semiconductor memory module would limit the installation space for installing the passive components 5, such as decoupling capacitors, and the space for routing the data signal lines to the semiconductor memory chips to an excessive degree, not to mention the increased number of pins.